The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2016

Filed:

Dec. 18, 2012
Applicant:

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Inventors:

Jung Tae Jeong, Icheon-si, KR;

Il Hwan Cho, Icheon-si, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/04 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 23/13 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/64 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); H01L 23/13 (2013.01); H01L 23/481 (2013.01); H01L 23/49805 (2013.01); H01L 23/64 (2013.01); H01L 24/01 (2013.01); H01L 24/05 (2013.01); H01L 24/72 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/32225 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06551 (2013.01); H01L 2225/06565 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01);
Abstract

A semiconductor package includes a substrate and a plurality of semiconductor chips stacked on the substrate. Each of the semiconductor chips has a front surface, a rear surface opposite to the front surface, a sidewall surface connecting the front surface to the rear surface, a vertical through electrode extending from the front surface toward the rear surface with a predetermined depth, and a horizontal through electrode laterally extending from the sidewall surface to be connected to the vertical through electrode. At least one connection member is disposed on the sidewall surfaces of the semiconductor chips to connect the horizontal through electrodes of the semiconductor chips to each other. Related methods are also provided.


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