The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2016

Filed:

Apr. 25, 2013
Applicant:

Lapis Semiconductor Co., Ltd., Yokohama, JP;

Inventors:

Kengo Takemasa, Miyazaki, JP;

Yuichi Yoshida, Miyazaki, JP;

Toshihisa Sone, Yokohama, JP;

Kazuya Yamada, Yokohama, JP;

Akihiro Takei, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B 5/32 (2006.01); H01L 41/08 (2006.01); H01L 23/495 (2006.01); H03L 1/02 (2006.01); H01L 23/34 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01L 23/34 (2013.01); H01L 23/49541 (2013.01); H01L 23/49596 (2013.01); H03L 1/022 (2013.01); H01L 21/565 (2013.01); H01L 23/3107 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/49171 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/3025 (2013.01);
Abstract

A semiconductor device includes a lead frame, an oscillator, an integrated circuit and first bonding wires. The oscillator includes plural terminals separated from each other by a predetermined distance, and that is mounted to an oscillator mounting region formed on a first face of the lead frame. The oscillator mounting region has a narrower width than the distance between the plural terminals. The integrated circuit is mounted to a second face of the lead frame, which is on an opposite side to the first face. The first bonding wires connect the plural terminals of the oscillator to terminals of the integrated circuit.


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