The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2016

Filed:

Apr. 22, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Edgar R. Cordero, Round Rock, TX (US);

Timothy J. Dell, Colchester, VT (US);

Joab D. Henderson, Pflugerville, TX (US);

Jeffrey A. Sabrowski, Leander, TX (US);

Anuwat Saetow, Austin, TX (US);

Saravanan Sethuraman, Bangalore, IN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/44 (2006.01); G11C 29/42 (2006.01); G06F 11/10 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 29/4401 (2013.01); G06F 11/1048 (2013.01); G11C 29/42 (2013.01); G11C 29/702 (2013.01); G11C 2029/0411 (2013.01); G11C 2029/4402 (2013.01);
Abstract

A method, system and computer program product are provided for implementing ECC (Error Correction Codes) redundancy using reconfigurable logic blocks in a computer system. When a fail is detected when reading from memory, it is determined if the incorrect data is in the data or the ECC component of the data. When incorrect data is found in the ECC component of the data, and an actionable threshold is not reached, a predetermined Reliability, Availability, and Serviceability (RAS) action is taken. When the actionable threshold is reached with incorrect data identified in the ECC component of the data, an analysis process is performed to determine if the ECC logic is faulty. When a fail in the ECC logic is detected, the identified ECC failed logic is replaced with a spare block of logic.


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