Weak erase of a dummy memory cell to counteract inadvertent programming

Abstract

A NAND string includes dummy memory cells between data memory cells and source-side and drain-side select gates. A gradual increase in threshold voltage (Vth) for the dummy memory cells which occurs due to program-erase cycles is periodically detected by a read operation at an upper checkpoint voltage. If the Vth has increased beyond the checkpoint, the control gate voltage of the dummy memory cells is decreased during subsequent erase operations of program-erase cycles, causing a gradual weak erase. A decrease in the Vth is later detected by a read operation at a lower checkpoint voltage. If the Vth has decreased too much, the control gate voltage is raised during subsequent erase operations, causing a gradual weak programming. The process can be repeated to keep the Vth within a desired range and avoid disturbs due to an increase in a channel voltage gradient which would otherwise occur.