The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2016

Filed:

Sep. 09, 2014
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Shahid Ahmad Butt, Ossining, NY (US);

Pamela Castalino, Hopewell Junction, NY (US);

Harold Pilo, Underhill, VT (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01);
Abstract

Transistors are connected to ground outside of an SRAM array column. One transistor is connected from VSS to ground on the Q side of an SRAM cell. Another transistor is connected from VSS to ground on the Q' (Q complement) side of an SRAM cell. Each transistor is gated by is complementary bit line. The Q side transistor is gated by the BL′ (bit line complement, or 'BLC') line, and the Q′ side is gated by the BL line. The ground of the complement side is disconnected during a write operation to increase the performance of a state change during a write operation where a logical one is written to the Q node, thus improving write margin.


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