The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2016

Filed:

Jul. 02, 2014
Applicant:

Dell Products, Lp, Round Rock, TX (US);

Inventors:

Gregory J. McHale, Brookline, NH (US);

Brian G. Nadeau, Nashua, NH (US);

Brian K. Panner, Windham, NH (US);

Peter J. Hunter, Amherst, NH (US);

Damon Hsu-Hung, Sudbury, MA (US);

Janice Lacy, Temple, NH (US);

Assignee:

Dell Products, LP, Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 12/08 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0658 (2013.01); G06F 3/0604 (2013.01); G06F 3/0647 (2013.01); G06F 3/0685 (2013.01); G06F 12/0866 (2013.01); G06F 2003/0697 (2013.01); G06F 2212/217 (2013.01);
Abstract

In an embodiment, a hybrid storage array one uses two or more storage device tiers provided by solid state drives (SSDs) and hard disk drives (HDDs). Random writes are collected and written to a write cache extension, such as a portion of the SSD storage tier. The write cache extension absorbs such accesses that would otherwise be written to HDD storage directly. Data structures are created in a cache memory local to an array controller representing the location on the write cache extension to which the writes were committed and a location in the storage system where they were originally intended to go. The write cache extension can be enabled all of the time, or only when the array controller write cache experiences certain operating conditions, such as when its utilization exceeds a predetermined amount. The approach improves the overall performance of the hybrid array.


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