The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2016

Filed:

Nov. 24, 2014
Applicant:

Pmc-sierra Us, Inc., Sunnyvale, CA (US);

Inventors:

Mark Hiebert, New Westminster, CA;

Derek J. W. Ho, Vancouver, CA;

Assignee:

PMC-SIERRA US, INC., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/50 (2006.01); G04F 10/00 (2006.01); H03M 1/12 (2006.01); H04L 7/033 (2006.01); H03M 1/00 (2006.01);
U.S. Cl.
CPC ...
G04F 10/005 (2013.01); H03M 1/1255 (2013.01); H04L 7/0331 (2013.01); G04F 10/00 (2013.01); H03M 1/00 (2013.01); H03M 1/12 (2013.01); H03M 2201/4233 (2013.01);
Abstract

Provided is a method and apparatus for aligning a first local oscillator (LO) clock generated by a controllable LO clock generator in a first radio frequency (RF) path with a second LO clock in a second RF path. The apparatus includes a synchronization channel configured to exchange a synchronization clock between the first and second RF paths, a phase detector configured to measure a phase alignment between the first and second LO clocks, and a loop filter configured to drive the controllable LO clock generators using the phase alignment. Also provided is a time to digital converter. The time to digital converter includes a D flip-flop for sampling first and second input clocks with a third clock, and a counter configured to synchronously increment the resulting samples and create a digital proportional value representing the delay between the first and second clocks.


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