The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2015

Filed:

Dec. 27, 2011
Applicants:

Love Kothari, Sunnyvale, CA (US);

Mark Fullerton, Austin, TX (US);

Rajesh Rajan, Bangalore, IN;

Veronica Alarcon, San Jose, CA (US);

Inventors:

Love Kothari, Sunnyvale, CA (US);

Mark Fullerton, Austin, TX (US);

Rajesh Rajan, Bangalore, IN;

Veronica Alarcon, San Jose, CA (US);

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/02 (2006.01); H03L 7/08 (2006.01); H03K 3/03 (2006.01); H03K 3/037 (2006.01); H03K 19/01 (2006.01); G06F 12/14 (2006.01); G06F 21/44 (2013.01); H03K 5/13 (2014.01); H03L 7/097 (2006.01); H03L 7/099 (2006.01); G06F 1/32 (2006.01); G06F 1/26 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0802 (2013.01); G06F 1/32 (2013.01); G06F 12/14 (2013.01); G06F 21/44 (2013.01); H03K 3/0315 (2013.01); H03K 3/0375 (2013.01); H03K 5/133 (2013.01); H03K 19/01 (2013.01); H03L 7/097 (2013.01); H03L 7/0997 (2013.01); G06F 1/26 (2013.01); G06F 1/3203 (2013.01); G06F 1/3228 (2013.01); H01L 2924/0002 (2013.01); H03K 2005/00026 (2013.01); H03K 2005/00058 (2013.01);
Abstract

An electronics device is disclosed that reduces latency resulting from communication between a first electronics component operating based on a fast clock and a second electronics component operating based on a slow clock reduces communication latency. When transferring the data from the first component to the second, the data is written into a buffer using the first clock, and then extracted by the second component using the second clock. Alternatively, when transferring the data from the second component to the first component, the first component reads the data from the second component and monitors whether the data was extracted during a relevant edge of the second clock signal, in which case the first component again extracts the data from the second component.


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