The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 29, 2015
Filed:
Apr. 21, 2014
Qualcomm Incorporated, San Diego, CA (US);
Kenneth Arcudia, Cary, NC (US);
Zhiqin Chen, San Diego, CA (US);
QUALCOMM INCORPORATED, San Diego, CA (US);
Abstract
Systems and methods for generating clock phase signals with accurate timing relations are disclosed. For example, four clock signals spaced by 90 degrees can be generating from differential CML clock signals. A CML to CMOS converter converts the differential CML clock signals to differential CMOS clock signals and provides duty cycle correction. Delay cells produce delayed clock signals from the differential CMOS clock signals. The differential CMOS clock signals and the delayed clock signals are logically combined to produce four quarter clock signals having active times of one-quarter clock period. Set-reset latches produce the four clock signals from the quarter clock signals. A calibration module control delays of the delay cells and controls the duty cycle correction of the CML to CMOS converter to adjust the timing relationships of the four clock signals. The four clock signals may be used, for example, in a deserializer.