The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2015

Filed:

Dec. 26, 2013
Applicant:

Samsung Display Co., Ltd., Yongin, KR;

Inventor:

Bong-Won Lee, Seoul, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/84 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66477 (2013.01); H01L 27/1288 (2013.01); H01L 29/66765 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78618 (2013.01);
Abstract

Disclosed is a method of manufacturing an oxide semiconductor device, including: forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode; forming an active pattern on the gate insulating layer; forming a first mask pattern on the gate insulating layer and the active pattern; forming an insulating interlayer on the gate insulating layer, the active pattern, and the first mask pattern; forming a second mask pattern on the insulating interlayer, the second mask pattern comprising an opening that exposes a region where the first mask pattern is formed; forming contact holes exposing portions of the active pattern by patterning the insulating interlayer using the first mask pattern and the second mask pattern; and forming a source electrode and a drain electrode on the gate insulating layer by filling the contact holes, the drain electrode spaced apart from the source electrode.


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