The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2015

Filed:

Sep. 18, 2014
Applicants:

Jae-gwon Jang, Hwaseong-si, KR;

Jin-woo Park, Seoul, KR;

Jong-ho Lee, Hwaseong-si, KR;

Inventors:

Jae-Gwon Jang, Hwaseong-si, KR;

Jin-Woo Park, Seoul, KR;

Jong-Ho Lee, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 29/82 (2006.01); H01L 21/00 (2006.01); H01L 23/00 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/564 (2013.01); H01L 21/78 (2013.01); H01L 23/3142 (2013.01); H01L 24/48 (2013.01); H01L 24/50 (2013.01); H01L 24/86 (2013.01); H01L 2224/85005 (2013.01);
Abstract

A method of manufacturing a semiconductor package having a magnetic shield function is provided. The method includes forming cracks in a lattice structure on an active surface in which electrode terminals are formed; grinding a back surface of a wafer facing the active surface, bonding a tape on the active surface of the wafer, expanding the tape such that the wafer on the tape is divided as semiconductor chips, forming a shield layer on surfaces of the semiconductor chips and the tape, cutting the shield layer between the semiconductor chips and individualizing as each of the semiconductor chips which has a first shield pattern formed on back surface and sides, bonding the semiconductor chips on a substrate, and forming a second shield pattern on each of the active surfaces of the semiconductor chips, wherein the semiconductor chips and the substrate are physically and electrically connected by a bonding wire.


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