The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2015

Filed:

Jan. 19, 2012
Applicants:

Yoann Guillemenet, Crest, FR;

Lionel Torres, Combaillaux, FR;

Inventors:

Yoann Guillemenet, Crest, FR;

Lionel Torres, Combaillaux, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G11C 11/15 (2006.01); G11C 11/16 (2006.01); H03K 19/177 (2006.01); G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
G11C 13/003 (2013.01); G11C 11/15 (2013.01); G11C 11/16 (2013.01); G11C 11/412 (2013.01); G11C 13/0002 (2013.01); H03K 19/1776 (2013.01);
Abstract

A memory device includes at least one memory cell having a first transistor coupled between a first storage node and a first supply voltage; a second transistor coupled between a second storage node and the first supply voltage and a single resistance switching element. Control terminals of the first and second transistors are coupled to the second and first storage nodes respectively. The single resistive switching element is coupled in series with the first transistor and is programmable to have one of first and second resistances. The first storage node is coupled to a first access line via a third transistor connected to said first storage node, and the second storage node is coupled to a second access line via a fourth transistor connected to the second storage node.


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