The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2015

Filed:

Jun. 29, 2012
Applicants:

Ravindraraj Ramaraju, Round Rock, TX (US);

George P. Hoekstra, Austin, TX (US);

Andrew C. Russell, Austin, TX (US);

Inventors:

Ravindraraj Ramaraju, Round Rock, TX (US);

George P. Hoekstra, Austin, TX (US);

Andrew C. Russell, Austin, TX (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/10 (2006.01); G11C 8/10 (2006.01); G11C 11/418 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1075 (2013.01); G11C 8/10 (2013.01); G11C 11/418 (2013.01);
Abstract

A memory having a memory array having a plurality of word lines, a plurality of bit cells coupled to the word lines, and a plurality of control memory cells coupled to the word lines. Each word line of the plurality of word lines has a control memory cell coupled thereto and each control memory cell has an output. The memory also has a plurality of logic circuits coupled to the plurality of word lines. The output of each control memory cell is coupled to a corresponding one of the plurality of logic circuits. The plurality of logic circuits prevents access to the word line selected by a row address if the output of the control memory cell coupled to the selected word line is in a first logic state.


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