The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2015

Filed:

Mar. 04, 2014
Applicant:

Vmware, Inc., Palo Alto, CA (US);

Inventors:

Carl A. Waldspurger, Palo Alto, CA (US);

Rajesh Venkatasubramanian, San Jose, CA (US);

Alexander Thomas Garthwaite, Hamilton, MA (US);

Yury Baskakov, Newton, MA (US);

Puneet Zaroo, Santa Clara, CA (US);

Assignee:

VMware, Inc., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/12 (2006.01); G06F 9/455 (2006.01); G06F 11/34 (2006.01);
U.S. Cl.
CPC ...
G06F 12/122 (2013.01); G06F 9/45558 (2013.01); G06F 11/3471 (2013.01); G06F 12/123 (2013.01); G06F 2009/45583 (2013.01); G06F 2201/815 (2013.01); G06F 2201/88 (2013.01);
Abstract

Miss rate curves are constructed in a resource-efficient manner so that they can be constructed and memory management decisions can be made while the workloads are running. The resource-efficient technique includes the steps of selecting a subset of memory pages for the workload, maintaining a least recently used (LRU) data structure for the selected memory pages, detecting accesses to the selected memory pages and updating the LRU data structure in response to the detected accesses, and generating data for constructing a miss-rate curve for the workload using the LRU data structure. After a memory page is accessed, the memory page may be left untraced for a period of time, after which the memory page is retraced.


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