The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2015

Filed:

Sep. 17, 2010
Applicants:

Weiqi Ding, Fremont, CA (US);

Sergey Shumarayev, Los Altos Hills, CA (US);

Mingde Pan, Morgan Hill, CA (US);

Peng LI, Palo Alto, CA (US);

Masashi Shimanouchi, San Jose, CA (US);

Inventors:

Weiqi Ding, Fremont, CA (US);

Sergey Shumarayev, Los Altos Hills, CA (US);

Mingde Pan, Morgan Hill, CA (US);

Peng Li, Palo Alto, CA (US);

Masashi Shimanouchi, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/02 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31709 (2013.01);
Abstract

An IC that includes a jitter generator, where the jitter generator is integral with the IC and generates non-intrinsic jitter, is provided. In one implementation, the non-intrinsic jitter is used to measure a characteristic of the IC. In one implementation, the non-intrinsic jitter is used to test jitter tolerance of the IC. In yet another implementation, the non-intrinsic jitter is used to test another IC coupled to the IC that includes the jitter generator.


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