The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 29, 2015
Filed:
Oct. 30, 2013
Xiaoxiao Wang, Austin, TX (US);
Orman G. Shofner, Cedar Park, TX (US);
Dat T. Tran, Round Rock, TX (US);
Leroy Winemberg, Austin, TX (US);
Ender Yilmaz, Austin, TX (US);
Xiaoxiao Wang, Austin, TX (US);
Orman G. Shofner, Cedar Park, TX (US);
Dat T. Tran, Round Rock, TX (US);
Leroy Winemberg, Austin, TX (US);
Ender Yilmaz, Austin, TX (US);
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Abstract
System circuitry includes a logic circuit having an input and an output that is a functional element of the system circuitry. Pattern application circuitry is coupled to the input of the logic circuit and provides an input pattern to the input of the logic circuit. The input pattern has a valid signature based upon a comparison of the input and the output of the logic circuit when the logic circuit is functioning properly. A logic comparator is coupled to the input and the output of the logic circuit and generates pulses in response to the input pattern. A counter is coupled to the logic comparator that obtains a count of the pulses generated by the logic comparator in response to the input pattern. A signature comparator is coupled to the counter and generates a warning signal if the valid signature is different from the count.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile