The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2015

Filed:

Jul. 30, 2012
Applicants:

Wei HU, Suzhou, CN;

Gang LI, Suzhou, CN;

Jia-xin Mei, Suzhou, CN;

Inventors:

Wei Hu, Suzhou, CN;

Gang Li, Suzhou, CN;

Jia-Xin Mei, Suzhou, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B81C 1/00 (2006.01); H04R 31/00 (2006.01); H04R 19/00 (2006.01);
U.S. Cl.
CPC ...
B81C 1/00158 (2013.01); B81C 1/00246 (2013.01); H04R 19/005 (2013.01); H04R 31/00 (2013.01);
Abstract

A method for integrating an IC and a MEMS component includes the following steps: S1) providing a SOI base () having a first area () and a second area (); S2) fabricating an IC on the first area through a standard semiconductor process, and simultaneously forming a metal conductive layer () and a medium insulation layer () extending to the second area; S3) partly removing the medium insulation layer and then further partly removing the silicon component layer so as to form a backplate diagram; S4) depositing a sacrificial layer () above the SOI base; S5) forming a Poly Sil-xGex film () on the sacrificial layer; S6) forming a back cavity (); and S7) eroding the sacrificial layer to form a chamber () in communication with the back cavity. Besides, a chip () fabricated by the above method is also disclosed.


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