The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2015

Filed:

Aug. 29, 2014
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Rainer Stuhlberger, Puchenau, AT;

Klemens Kordik, Linz, AT;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/197 (2006.01); H03C 3/09 (2006.01); H03L 7/085 (2006.01); G01S 13/88 (2006.01);
U.S. Cl.
CPC ...
H03L 7/1976 (2013.01); H03C 3/0933 (2013.01); H03L 7/197 (2013.01); H03L 7/1974 (2013.01); G01S 13/88 (2013.01); H03L 7/085 (2013.01);
Abstract

An RF transceiver circuit is disclosed herein. In accordance with one example of the disclosure the RF transceiver circuit includes a phase-locked-loop (PLL) with a fractional-N multi-modulus divider. The PLL operates in accordance with a PLL clock frequency and generates a frequency modulated RF output signal. The RF transceiver circuit further includes a modulator unit, which is configured to generate a sequence of division values dependent on a set of modulation parameters. The modulator operates in accordance with a system clock frequency, which is lower than the PLL clock frequency. A sample rate conversion unit is coupled between the modulator unit and a fractional-N multi-modulus divider. The sample rate conversion unit is configured to interpolate the sequence of division ratios to provide an interpolated sequence of division ratios at a rate corresponding to the PLL clock frequency.


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