The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9219238 B1

PDF
Full Text
Expired
Date of Patent:
Dec. 22, 2015

Filed:

Dec. 14, 2012
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventor:

Xuehui Zhang, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 51/05 (2006.01); H01L 27/28 (2006.01); H01L 27/32 (2006.01); H01L 51/10 (2006.01); G02F 1/1362 (2006.01);
U.S. Cl.
CPC ...
H01L 51/0512 (2013.01); G02F 1/136286 (2013.01); H01L 27/283 (2013.01); H01L 27/3274 (2013.01); H01L 51/10 (2013.01); H01L 51/0541 (2013.01);
Abstract

Disclosed is an organic thin film transistor array substrate and a method for manufacturing. The method increases the manufacturing efficiency of the organic thin film transistor array substrate. In the method, a pixel electrode, a source electrode, a data line and a drain electrode are formed on a substrate through one patterning process, where both of the pattern layer for the source electrode and the pattern layer for the data line and the drain electrode are located above the pixel electrode. An organic semiconductor layer and a gate insulating layer that covers the organic semiconductor layer are formed through one patterning process, where the organic semiconductor layer covers both of the pattern layer for the source electrode and the pattern layer for the data line and the drain electrode. A gate electrode and a gate line are formed through one patterning process on the substrate formed with the gate insulating layer.


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