The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 22, 2015
Filed:
Nov. 01, 2013
Applicant:
Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;
Inventors:
Hiroshi Shibata, Yamagata, JP;
Shinji Maekawa, Kanagawa, JP;
Assignee:
Semiconductor Energy Laboratory Co., LTD., Kanagawa-ken, JP;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/786 (2006.01); G02F 1/1362 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); G02F 1/1345 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78633 (2013.01); G02F 1/136209 (2013.01); G02F 1/136286 (2013.01); H01L 27/1255 (2013.01); H01L 29/66757 (2013.01); H01L 29/78621 (2013.01); H01L 29/78645 (2013.01); H01L 29/78675 (2013.01); H01L 29/78696 (2013.01); G02F 1/13454 (2013.01); G02F 1/136213 (2013.01); G02F 1/136227 (2013.01); G02F 2202/105 (2013.01);
Abstract
A multi-gate structure is used and a width (d1) of a high concentration impurity region sandwiched by two channel forming regions in a channel length direction is set to be shorter than a width (d2) of low concentration impurity regions in the channel length direction. Thus, a resistance of the entire semiconductor layer of a TFT which is in an on state is reduced to increase an on current. In addition, a carrier life time due to photoexcitation produced in the high concentration impurity region can be shortened to reduce light sensitivity.