The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2015

Filed:

Mar. 19, 2013
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventors:

Shoichi Miyazaki, Yokkaichi, JP;

Koichi Matsuno, Mie-gun, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/70 (2006.01); H01L 21/20 (2006.01); H01L 27/105 (2006.01); H01L 27/115 (2006.01); H01L 21/764 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1052 (2013.01); H01L 21/764 (2013.01); H01L 21/7682 (2013.01); H01L 21/76837 (2013.01); H01L 27/11524 (2013.01);
Abstract

Method of manufacturing a semiconductor device includes forming, in a first region, a first trench through a second gate electrode film and an interelectrode insulating film, and a second trench partially extending into a sacrificial film in an isolation trench, filling the second trench with a first insulating film; forming a third gate electrode film above the second gate electrode film and into the first trench such that the third gate electrode film contacts the first gate electrode film; etching the third and the second gate electrode film, the interelectrode insulating film, and the first gate electrode film to form select gate electrodes in the first region and a group of memory-cell gate electrodes in the second region; removing the sacrificial film; and forming a second insulating film over the element regions and the isolation trench to define an unfilled gap in the isolation trench below the memory-cell gate electrodes.


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