The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2015

Filed:

Nov. 12, 2014
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Henry E. Styles, Menlo Park, CA (US);

Jeffrey M. Fifield, Boulder, CO (US);

Ralph D. Wittig, Menlo Park, CA (US);

Philip B. James-Roxby, Longmont, CO (US);

Sonal Santan, San Jose, CA (US);

Devadas Varma, Los Altos, CA (US);

Fernando J. Martinez Vallina, Sunnyvale, CA (US);

Sheng Zhou, San Jose, CA (US);

Charles Kwah-Wah Lo, Toronto, CA;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/505 (2013.01);
Abstract

OpenCL program compilation may include generating, using a processor, a register transfer level (RTL) description of a first kernel of a heterogeneous, multiprocessor design and integrating the RTL description of the first kernel with a base platform circuit design. The base platform circuit design provides a static interface within a programmable integrated circuit to a host of the heterogeneous, multiprocessor design. A first configuration bitstream may be generated from the RTL description of the first kernel using the processor. The first configuration bitstream specifies a hardware implementation of the first kernel and supporting data for the configuration bitstream. The first configuration bitstream and the supporting data may be included within a binary container.


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