The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2015

Filed:

May. 29, 2012
Applicants:

Eric Nestler, Harvard, MA (US);

Vladimir Zlatkovic, Belmont, MA (US);

Inventors:

Eric Nestler, Harvard, MA (US);

Vladimir Zlatkovic, Belmont, MA (US);

Assignee:

Analog Devices, Inc., Norwood, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 27/26 (2006.01); G06F 17/14 (2006.01); G06G 7/19 (2006.01); G01D 5/24 (2006.01); G01R 31/02 (2006.01);
U.S. Cl.
CPC ...
G06F 17/14 (2013.01); G01R 27/2605 (2013.01); G06G 7/19 (2013.01); G01D 5/24 (2013.01); G01R 31/028 (2013.01);
Abstract

Some general aspects of the invention relate to a circuit and to a method for analog computation, for example, using switched capacitor integrated circuits. In some examples, a circuit includes a first group of capacitors and a second group of capacitors that may store charges during circuit operation. The first and/or the second group of capacitors may include multiple disjoint subsets of capacitors. An input circuit is provided for receiving a set of input signals and for inducing a charge on each of some or all capacitors in the first group of capacitors according to a corresponding input signal. Switches, for example, transistors controlled by a sequence of clock signals, are used to couple different sets of capacitors. Different configurations of the switches are used to form different sets of the capacitors among which charge can redistribute.


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