The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2015

Filed:

Jun. 05, 2013
Applicant:

SK Hynix Memory Solutions Inc., San Jose, CA (US);

Inventors:

Nishant Patil, Sunnyvale, CA (US);

Derrick Preston Chu, Santa Clara, CA (US);

Nandan Sridhar, Santa Clara, CA (US);

Prasanthi Relangi, San Jose, CA (US);

Assignee:

SK Hynix memory solutions inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 12/10 (2013.01); G06F 3/061 (2013.01); G06F 3/0638 (2013.01);
Abstract

An access instruction which includes a logical block address (LBA) is received. A first-level table is accessed to obtain a first-level table entry associated with the LBA. From the first-level table entry, a location associated with a second-level table on solid state storage media is determined. The second-level table is accessed at the determined location to obtain a second-level table entry associated with the LBA. From the second-level table entry, a physical block address corresponding to the logical block address is determined.


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