Gate drive circuit and display device having the gate drive circuit

Abstract

A gate drive circuit in which multiple stages are connected together one after each other. An n-th stage includes a pull-up part, a carry part, a pull-down part, a switching part, a first maintaining part and a second maintaining part. The pull-up part outputs a high voltage of a first clock signal. The carry part outputs a high voltage of the first clock signal. The pull-down part pulls-down the n-th gate signal into a first low voltage. The switching part outputs a first signal synchronized with the first clock signal during an interval other than a high voltage output interval of the n-th carry signal. The first maintaining part maintains the n-th gate signal at the first low voltage in response to the first signal. The second maintaining part maintains the n-th gate signal at the first low voltage in response to a second signal.