The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 15, 2015
Filed:
Dec. 19, 2011
Claude Basso, Raleigh, NC (US);
Jean L. Calvignac, Raleigh, NC (US);
Chih-jen Chang, Research Triangle Park, NC (US);
Damon Philippe, Research Triangle Park, NC (US);
Natarajan Vaidhyanathan, Research Triangle Park, NC (US);
Colin B. Verrilli, Research Triangle Park, NC (US);
Fabrice Jean Verplanken, LaGuade, FR;
Claude Basso, Raleigh, NC (US);
Jean L. Calvignac, Raleigh, NC (US);
Chih-Jen Chang, Research Triangle Park, NC (US);
Damon Philippe, Research Triangle Park, NC (US);
Natarajan Vaidhyanathan, Research Triangle Park, NC (US);
Colin B. Verrilli, Research Triangle Park, NC (US);
Fabrice Jean Verplanken, LaGuade, FR;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A network processor includes first communication protocol ports that each support 'M' minimum size packet data path traffic on 'N' lanes at ‘S’ Gigabits per second (Gbps) and traffic with different communication protocol units on ‘n’ additional lanes at ‘s’ Gbps. The first communication protocol ports support access to an external coprocessor using parsing logic located in each of the first communication protocol ports. The parsing logic, during a parsing period, is configured to send a request to the external coprocessor at reception of a ‘M’ size packet and to receive a response from the external coprocessor. The parsing logic sends a request maximum ‘m’ size byte word to the external coprocessor on one of the additional lanes and receives a response maximum ‘m’ size byte word from the external coprocessor on the one of the additional lanes while complying with the equation N×S/M=<n×s/m.