The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2015

Filed:

Dec. 23, 2011
Applicants:

Chang Hyun Lee, Seoul, KR;

Chang Kun Park, Gyeonggi-do, KR;

Inventors:

Chang Hyun Lee, Seoul, KR;

Chang Kun Park, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/21 (2006.01); H03F 3/193 (2006.01); H03F 1/22 (2006.01); H03F 3/195 (2006.01); H03F 3/24 (2006.01); H03F 3/45 (2006.01);
U.S. Cl.
CPC ...
H03F 3/21 (2013.01); H03F 1/223 (2013.01); H03F 3/193 (2013.01); H03F 3/195 (2013.01); H03F 3/211 (2013.01); H03F 3/245 (2013.01); H03F 3/4508 (2013.01); H03F 3/45179 (2013.01); H03F 2003/45008 (2013.01); H03F 2200/451 (2013.01); H03F 2203/45318 (2013.01); H03F 2203/45364 (2013.01); H03F 2203/45394 (2013.01); H03F 2203/45562 (2013.01); H03F 2203/45638 (2013.01); H03F 2203/45644 (2013.01);
Abstract

Disclosed is a differential power amplifier using mode injection, which includes: a first transistor of which the gate receives a first signal and the source is connected to the ground; a second transistor of which the gate receives a second signal and the source is connected to the ground; a third transistor of which the source is connected to the source of the first transistor; a fourth transistor of which the source is connected to the source of the second transistor; a fifth transistor of which the source is connected with the drain of the first transistor and the drain is connected with a first output port and the drain of the third transistor; and a sixth transistor of which the source is connected with the drain of the second transistor and the drain is connected with a second output port and the drain of the fourth transistor.


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