The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2015

Filed:

Aug. 25, 2014
Applicants:

Ki Jeong Kim, Hwaseong-si, KR;

Jung Ik OH, Seongnam-si, KR;

Sung Soo Ahn, Yongin-si, KR;

Dae Hyun Jang, Suwon-si, KR;

Inventors:

Ki Jeong Kim, Hwaseong-si, KR;

Jung Ik Oh, Seongnam-si, KR;

Sung Soo Ahn, Yongin-si, KR;

Dae Hyun Jang, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/72 (2006.01); H01L 29/788 (2006.01); H01L 27/115 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7889 (2013.01); H01L 27/1157 (2013.01); H01L 27/11517 (2013.01); H01L 27/11563 (2013.01); H01L 27/11575 (2013.01); H01L 27/11582 (2013.01); H01L 29/7926 (2013.01);
Abstract

According to example embodiments, a memory device includes a substrate, a channel region on the substrate, a plurality of gate electrode layers stacked on each other on the substrate, and a plurality of contact plugs. The gate electrode layers are adjacent to the channel region and extend in one direction to define a pad region. The gate electrode layers include first and second gate electrode layers. The contact plugs are connected to the gate electrode layers in the pad region. At least one of the contact plugs is electrically insulated from the from the first gate electrode layer and electrically connected to the second gate electrode layer by penetrating through the first gate electrode layer.


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