High speed, low loss and high density power semiconductor packages (μmaxpak) with molded surface mount high speed device(s) and multi-chip architectures

Abstract

A new Power DFN and Power QFN package architecture that accommodates Bump-chip die and other components in cavities on the bottom-side of the matrix leadframe, and the technique is also applicable to laminated substrate packages like the BGA and LGA. The package is especially suited for high speed power compound semiconductor devices like GaN and SiC. The package enables single and multiple power switch configurations, and well controlled paralleling of high speed power die switches. It enables co-packaging of associated components like cascoded switchs, gate drivers, isolators and protection devices, which must be tightly coupled at high switching speeds. The architecture accommodates components on the top-side of the leadframe as well allowing for multi-chip functions with extremely low interconnect inductance and resistance, and higher circuit and power densities. The package architecture provides for lower package thermal resistance with parallel thermal paths from both sides of power die to the external bottom-side pads, and supplementary isolated and non-isolated top-side heat dissipation. These type packages use standard proven, reliable and cost effective materials & assembly techniques that are available at commercial contract assemblers. They minimizes NRE for special equipment, tooling and development, and reduces time to market.