A/d conversion circuit and solid-state imaging device

Abstract

In an A/D conversion circuit and a solid-state imaging device, a latch circuit is in a disable state until a first timing at which an output signal of a comparison unit has been inverted, and is in an enable state until a second timing at which a delay time of the inversion delay circuit has passed from the first timing. The latch circuit is in the enable state until the second timing according to comparison start in the comparison unit. The latch circuit latches an output signal of a delay unit at the second timing. A determination unit determines whether the latch circuit accurately latches the output signal of the delay unit, and outputs a signal indicating a determination result to a delay controller. The delay controller controls the delay time of the inversion delay circuit based on the determination result.