The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2015
Filed:
Jan. 23, 2013
Applicant:
Panasonic Corporation, Osaka, JP;
Inventors:
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 21/336 (2006.01); H01L 29/78 (2006.01); H01L 21/324 (2006.01); H01L 29/66 (2006.01); H01L 21/306 (2006.01); H01L 29/417 (2006.01); H01L 29/16 (2006.01); H01L 21/04 (2006.01); H01L 21/223 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 21/02378 (2013.01); H01L 21/02529 (2013.01); H01L 21/0455 (2013.01); H01L 21/223 (2013.01); H01L 21/30604 (2013.01); H01L 21/324 (2013.01); H01L 29/1608 (2013.01); H01L 29/41741 (2013.01); H01L 29/66068 (2013.01); H01L 29/66734 (2013.01);
Abstract
A method for manufacturing a semiconductor device includes the steps of: forming, on a principal face of a substrate, a semiconductor layer including a first semiconductor region of a first conductivity type; and forming, in the semiconductor layer, a trench having a bottom located in the first semiconductor region. The method further includes a step of forming a trench bottom impurity region being of a second conductivity type and covering the bottom of the trench by performing annealing to cause part of the semiconductor layer corresponding to an upper corner portion of the trench to move to be placed on the bottom of the trench.