The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2015

Filed:

Feb. 21, 2013
Applicants:

Santhosh Kumar, Bangalore, IN;

Smitha Naganna, Bangalore, IN;

Deepak Pancholi, Bangalore, IN;

Inventors:

Santhosh Kumar, Bangalore, IN;

Smitha Naganna, Bangalore, IN;

Deepak Pancholi, Bangalore, IN;

Assignee:

SanDisk Technologies Inc., Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01G 4/232 (2006.01); H01L 49/02 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 28/60 (2013.01); H01G 4/232 (2013.01); H01L 23/5223 (2013.01); H01L 28/86 (2013.01); H01L 28/91 (2013.01); H01L 28/90 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A capacitor from a Metal-Oxide-Metal ('MoM') process may include a plurality of metal layers arranged with different design structures. The metal layers may be connected with vias. The metal layers may include wires, such as rows and/or fingers that are arranged for maximizing capacitance between adjacent fingers, as well as between fingers of different metal layers. As the spacing of the fingers is increased, the reliability, yield of final product, and ease of manufacturing both increase. The capacitor increases the spacing of wires/fingers while either maintaining or improving the capacitance per unit area.


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