The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2015
Filed:
May. 01, 2013
Sram well-tie with an uninterrupted grated first poly and first contact patterns in a bit cell array
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Anand Seshadri, Richardson, TX (US);
Steve Prins, Fairview, TX (US);
Russell McMullan, Allen, TX (US);
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 27/11 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); H01L 27/0207 (2013.01); H01L 27/11 (2013.01); H01L 2924/1437 (2013.01);
Abstract
An integrated circuit containing an SRAM may be formed using one or more periodic photolithographic patterns for elements of the integrated circuit such as gates and contacts, which have alternating line and space configurations in SRAM cells. Strap rows of the SRAM containing well ties and/or substrate taps which have SRAM cells on two opposite sides are configured so that the alternating line and space configurations are continuous across the regions containing the well ties and substrate taps.