The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2015

Filed:

Apr. 24, 2015
Applicant:

Fuji Electric Co., Ltd., Kanagawa, JP;

Inventors:

Motohito Hori, Nagano, JP;

Yoshikazu Takahashi, Nagano, JP;

Yoshinari Ikeda, Nagano, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0312 (2006.01); H01L 23/043 (2006.01); H01L 23/498 (2006.01); H01L 23/492 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/043 (2013.01); H01L 23/3107 (2013.01); H01L 23/492 (2013.01); H01L 23/49822 (2013.01); H01L 24/17 (2013.01); H01L 2224/16113 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/1203 (2013.01); H01L 2924/173 (2013.01); H01L 2924/1711 (2013.01); H01L 2924/1715 (2013.01);
Abstract

A power semiconductor module is equipped with: a frame made of an insulator; a first electrode plate made of a metal and fixed to a bottom opening of the frame; semiconductor chips electrically and physically connected to the first electrode plate; a multilayer substrate fixed to a principal surface of the first electrode plate; wiring members that electrically connect front surface electrodes of the semiconductor chips and a circuit plate of the multilayer substrate; a second electrode plate fixed to a top opening of the frame; and a metal block that has a first surface having a projected portion and a second surface disposed on a side opposite to the first surface and that is tapered from the first surface to the second surface, the projected portion being electrically and physically connected to the circuit plate of the multilayer substrate and the second surface being electrically and physically connected to the second electrode plate.


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