Memory controllers with dynamic port priority assignment capabilities

Abstract

A programmable integrated circuit may have a memory controller that interfaces between master modules and system memory. The memory controller may receive memory access requests from the masters via ports that have associated priority values and fulfill the memory access requests by configuring system memory to respond to the memory access requests. To dynamically modify the associated priority values while the memory controller receives and fulfills the memory access requests, a priority value update module may be provided that dynamically updates priority values for the memory controller ports. The priority value update module may provide the updated priority values with update registers that are updated based on an update signal and a system clock. The priority values may be provided by shift registers, memory mapped registers, or provided by masters along with each memory access request.