The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2015

Filed:

Aug. 09, 2013
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Ryan Shirlen, Wake Forest, NC (US);

Victor Wong, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/22 (2006.01); G06F 11/07 (2006.01); G06F 13/40 (2006.01); G01R 31/317 (2006.01); G06F 11/36 (2006.01); G06F 11/263 (2006.01); H04L 5/22 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0724 (2013.01); G01R 31/31705 (2013.01); G06F 11/2242 (2013.01); G06F 11/263 (2013.01); G06F 11/3656 (2013.01); G06F 13/4027 (2013.01); G06F 15/7807 (2013.01); H04L 5/22 (2013.01);
Abstract

Embodiments include apparatuses, systems, and methods for reduced pin cross triggering to enhance a debug experience. A time-division packetizing (TDP) technique may be employed to facilitate communication of triggers between integrated circuits (ICs) connected in series forming a TDP communication ring. The ICs on the TDP communication ring may each include a cross trigger interconnect structure for interpreting between trigger signals and hardware core instructions. The serial TDP communication across the ICs on the TDP communication ring allows the ICs to be connected in a manner that each cross trigger interconnect structure on each IC may function as if it were part of a single cross trigger interconnect structure across all of the ICs on the TDP communication ring. The individual ICs may operate asynchronously and a trigger clock may be passed along with other trigger data to implement the debugging techniques uniformly on each IC.


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