The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2015

Filed:

Feb. 19, 2014
Applicant:

Hitachi Kokusai Electric Inc., Tokyo, JP;

Inventors:

Hirohisa Yamazaki, Toyama, JP;

Satoshi Okada, Toyama, JP;

Tsutomu Kato, Toyama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); F16L 25/00 (2006.01); C23C 16/40 (2006.01); C23C 16/44 (2006.01); C23C 16/455 (2006.01);
U.S. Cl.
CPC ...
F16L 25/00 (2013.01); C23C 16/405 (2013.01); C23C 16/4405 (2013.01); C23C 16/4408 (2013.01); C23C 16/45527 (2013.01); C23C 16/45546 (2013.01); H01L 21/02271 (2013.01);
Abstract

Substrate processing uniformity is improved in the surfaces of wafers and between the wafers. A method of manufacturing a semiconductor device, including: loading a substrate holder into an inner tube, the substrate holder holding a plurality of substrates in a state where the plurality of substrates are horizontally oriented and stacked; forming thin films on the plurality of substrates by supplying a source gas to an inside of the inner tube; and unloading the substrate holder from the inner tube, wherein the forming the thin films is performed in a state where a conductance of a space between an inner wall of the inner tube and a gas penetration preventing cylinder is smaller than a conductance of a region where the plurality of substrates are stacked.


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