The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2015

Filed:

Apr. 26, 2011
Applicants:

Tomohiro Takahashi, Kanagawa, JP;

Hiroki Ui, Tokyo, JP;

Junichi Inutsuka, Kanagawa, JP;

Nozomu Takatori, Nagasaki, JP;

Inventors:

Tomohiro Takahashi, Kanagawa, JP;

Hiroki Ui, Tokyo, JP;

Junichi Inutsuka, Kanagawa, JP;

Nozomu Takatori, Nagasaki, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 5/335 (2011.01); H04N 5/378 (2011.01); H04N 5/3745 (2011.01); H03M 1/50 (2006.01); H03M 1/12 (2006.01); H03M 1/14 (2006.01); H03M 1/56 (2006.01); H03M 1/60 (2006.01);
U.S. Cl.
CPC ...
H04N 5/378 (2013.01); H03M 1/502 (2013.01); H04N 5/3745 (2013.01); H03M 1/123 (2013.01); H03M 1/14 (2013.01); H03M 1/56 (2013.01); H03M 1/60 (2013.01);
Abstract

An integrating A/D converter includes: a comparator comparing an input voltage to a reference voltage having a ramp waveform, a voltage value of which linearly varies with time; a higher-order bit counter starting operation or stopping operation triggered by inversion of an output signal of the comparator and outputting higher order bits by performing counting in a cycle of a clock signal; and a time-to-digital converter latching phase information of the clock signal corresponding to plural signals obtained by delaying an output signal of the comparator and decoding the latched values to output lower order bits having higher resolution than the clock cycle.


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