The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2015

Filed:

Apr. 26, 2013
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Cristiano Gianluca Stella, San Gregorio di Catania, IT;

Gaetano Pignataro, Trecastagni, IT;

Maurizio Maria Ferrara, Catania, IT;

Assignee:

STMicroelectronics S.r.l., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 25/07 (2006.01); H01L 23/433 (2006.01); H01L 23/492 (2006.01); H01L 23/495 (2006.01);
U.S. Cl.
CPC ...
H01L 23/34 (2013.01); H01L 23/4334 (2013.01); H01L 23/492 (2013.01); H01L 23/49562 (2013.01); H01L 23/49568 (2013.01); H01L 23/49575 (2013.01); H01L 25/074 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13062 (2013.01); H01L 2924/13091 (2013.01);
Abstract

A power device includes a chip of semiconductor material and a further chip of semiconductor material on each of which at least one power transistor is integrated; each chip comprises a first conduction terminal on a first surface, and a second conduction terminal and a control terminal on a second surface opposite the first surface, and an insulating body embedding said chip and said further chip. In the solution according to one or more embodiments of the present disclosure, the first surface of said chip faces the second surface of said further chip, and the power device further comprises a first heat-sink arranged between said chip and said further chip and electrically coupled with the first conduction terminal of said chip and with the second conduction terminal of said further chip, the control terminal of said further chip being electrically insulated from the first heat-sink.


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