The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2015

Filed:

Dec. 04, 2013
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Mayumi Yamamoto, Yokohama, JP;

Koki Ueno, Yokohama, JP;

Yuzuru Shibazaki, Fujisawa, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/12 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 16/0483 (2013.01); G11C 16/12 (2013.01); G11C 16/3427 (2013.01);
Abstract

A nonvolatile semiconductor memory device including: a memory cell array including NAND strings; a plurality of word lines; a plurality of bit lines; a source line; and a control circuit configured to execute a write operation. The control circuit is configured to, when charging an unselected memory string prior to the write operation, execute both first and second charging operations, the first charging operation applying to the bit line connected to the unselected memory string a first voltage and rendering conductive a first select transistor to charge the unselected memory string, and the second charging operation applying to the source line connected to the unselected memory string a second voltage and rendering conductive a second select transistor to charge the unselected memory string, the first and second charging operations being executed at different timings.


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