The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2015

Filed:

Oct. 30, 2014
Applicant:

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Inventors:

Yeon Uk Kim, Icheon-si, KR;

Jeong Tae Hwang, Icheon-si, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/41 (2006.01); G11C 11/418 (2006.01); G11C 17/18 (2006.01); G11C 17/16 (2006.01);
U.S. Cl.
CPC ...
G11C 11/418 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01);
Abstract

The semiconductor device includes a power control signal generator, a fuse controller and a fuse array portion. The power control signal generator generates a power control signal enabled during a predetermined period from a termination moment of a power-up period and enabled in response to a test mode signal. The fuse controller generates a boot-up signal enabled if a reboot-up signal is inputted during an enablement period of the power control signal. The fuse controller also generates a fuse reset signal enabled if a reset signal is inputted after a clock training operation. The fuse array portion generates a plurality of fuse data initialized if the fuse reset signal is enabled. The plurality of fuse data are programmed according to electrical open/short states of fuses in response to the power control signal.


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