The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2015

Filed:

Sep. 07, 2012
Applicants:

Shuuichi Senou, Kanagawa, JP;

Kenjyu Shimogawa, Kanagawa, JP;

Susumu Takano, Kanagawa, JP;

Toshihiko Funaki, Kanagawa, JP;

Hideaki Arima, Kanagawa, JP;

Inventors:

Shuuichi Senou, Kanagawa, JP;

Kenjyu Shimogawa, Kanagawa, JP;

Susumu Takano, Kanagawa, JP;

Toshihiko Funaki, Kanagawa, JP;

Hideaki Arima, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/36 (2006.01); G11C 7/22 (2006.01); G06F 13/40 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G11C 7/22 (2013.01); G06F 3/0635 (2013.01); G06F 13/4022 (2013.01);
Abstract

A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit, a first memory core that operates based on the first mode information, the first memory core being connected to the first bus-interface circuit and supplied with a first clock signal, a second memory core, the second memory core being supplied with a second clock signal and a select circuit that selectively connects the second memory core to the first or second bus-interface circuit based on predetermined switching information, in which the second memory core operates based on the second mode information when the second memory core is connected to the second bus-interface circuit.


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