The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2015

Filed:

Mar. 02, 2015
Applicant:

Silicon Space Technology Corporation, Austin, TX (US);

Inventors:

Wesley H. Morris, Austin, TX (US);

David R. Gifford, Pflugerville, TX (US);

Rex E. Lowther, Palm Bay, FL (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); G06F 11/10 (2006.01); G06F 11/07 (2006.01); G11C 8/00 (2006.01); H03K 19/003 (2006.01); G06F 11/18 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1008 (2013.01); G06F 11/0793 (2013.01); G06F 11/1048 (2013.01); G06F 11/186 (2013.01); G11C 8/00 (2013.01); H03K 19/00392 (2013.01); G06F 11/183 (2013.01);
Abstract

An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry.


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