The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 01, 2015
Filed:
Oct. 12, 2012
Altera Corporation, San Jose, CA (US);
Nagesh Vodrahalli, Los Altos, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Techniques for electrically testing an integrated circuit (IC) die with a partially completed and validated module (module) include providing an IC die to be tested on an IC package substrate of a validated test module, the positioned IC die and the module forming a multi-die flip-chip test assembly, and without attaching the interconnection bumps of the IC die to the package pads of the module, electrically testing the multi-die flip-chip test assembly. The method may further involve, responsive to the multi-die flip-chip test assembly passing electrical testing positioning the IC die on a production IC package substrate and attaching the IC die to the production IC package substrate. Corresponding apparatus and systems can also be used to perform the technique.