The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 24, 2015
Filed:
Jan. 21, 2014
Applicant:
Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;
Inventor:
Hiroshi Matsumura, Isehara, JP;
Assignee:
FUJITSU LIMITED, Kawasaki, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 7/185 (2006.01); H03L 7/085 (2006.01); H03L 7/07 (2006.01); G01S 7/40 (2006.01); G01S 13/34 (2006.01); G01S 13/44 (2006.01); G01S 13/93 (2006.01);
U.S. Cl.
CPC ...
H03L 7/085 (2013.01); G01S 7/4056 (2013.01); G01S 13/345 (2013.01); H03L 7/07 (2013.01); G01S 13/44 (2013.01); G01S 13/931 (2013.01); G01S 2007/4065 (2013.01); G01S 2007/4091 (2013.01);
Abstract
An electronic circuit includes a first PLL circuit including a first frequency divider whose frequency-division ratio is variably controlled, a second frequency divider configured to divide a frequency of a signal input into the first frequency divider, a delay circuit configured to delay an output signal of the second frequency divider, a second PLL circuit configured to receive an output signal of the delay circuit as a reference signal, and a mixer circuit configured to receive as inputs an oscillating signal of the first PLL circuit and an oscillating signal of the second PLL circuit.