The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2015

Filed:

Mar. 26, 2013
Applicant:

Nichia Corporation, Anan-shi, Tokushima, JP;

Inventors:

Yoshikazu Matsuda, Komatsushima, JP;

Kazuto Okamoto, Tokushima, JP;

Assignee:

NICHIA CORPORATION, Anan-shi, Tokushima, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/76 (2006.01); H01L 33/32 (2010.01); H01L 33/00 (2010.01); H01L 33/20 (2010.01); H01L 33/64 (2010.01);
U.S. Cl.
CPC ...
H01L 33/32 (2013.01); H01L 33/0075 (2013.01); H01L 33/0079 (2013.01); H01L 33/0095 (2013.01); H01L 33/20 (2013.01); H01L 33/642 (2013.01);
Abstract

Disclosed is a vertical nitride semiconductor device including a conductive substrate; a semiconductor layer bonded to the conductive substrate via a second electrode; a metal layer formed on the conductive substrate; a first electrode formed on the semiconductor layer; and a bonding layer formed between the conductive substrate and the second electrode. The conductive substrate has a flange part, which extends from a side surface of the conductive substrate, on a side of the other front surface thereof. The flange part is formed in a manner in which the conductive substrate and the semiconductor layer are bonded together and then a remaining part of the conductive substrate is divided, the remaining part being formed by cutting off the semiconductor layer and part of the conductive substrate in a thickness direction so as to expose a side surface of the semiconductor layer and the side surface of the conductive substrate.


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