The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2015

Filed:

Apr. 11, 2013
Applicants:

Masatoshi Yokoyama, Tochigi, JP;

Tsutomu Murakawa, Isehara, JP;

Kenichi Okazaki, Tochigi, JP;

Masayuki Sakakura, Isehara, JP;

Takuya Matsuo, Osaka, JP;

Akihiro Oda, Osaka, JP;

Shigeyasu Mori, Osaka, JP;

Yoshitaka Yamamoto, Yamatokoriyama, JP;

Inventors:

Masatoshi Yokoyama, Tochigi, JP;

Tsutomu Murakawa, Isehara, JP;

Kenichi Okazaki, Tochigi, JP;

Masayuki Sakakura, Isehara, JP;

Takuya Matsuo, Osaka, JP;

Akihiro Oda, Osaka, JP;

Shigeyasu Mori, Osaka, JP;

Yoshitaka Yamamoto, Yamatokoriyama, JP;

Assignees:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Sharp Kabushiki Kaisha, Osaka-shi, Osaka, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7869 (2013.01);
Abstract

Provided is a semiconductor device in which generation of a parasitic channel in an end region of an oxide semiconductor film is suppressed. The semiconductor device includes a gate electrode, an oxide semiconductor film, a source electrode and a drain electrode, and a channel region formed in the oxide semiconductor film. The channel region is formed between a first side surface of the source electrode and a second side surface of the drain electrode opposite to the first side surface. The oxide semiconductor film has an end region which does not overlap with the gate electrode. The end region which does not overlap with the gate electrode is positioned between a first region that is the nearest to one end of the first side surface and a second region that is the nearest to one end of the second side surface.


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