The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2015

Filed:

Sep. 26, 2014
Applicants:

Boe Technology Group Co., Ltd., Bejing, CN;

Beijing Boe Optoelectronics Technology Co., Ltd., Beijing, CN;

Inventors:

Wenyu Zhang, Beijing, CN;

Zhenyu Xie, Beijing, CN;

Jian Guo, Beijing, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 21/027 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); G02F 1/1368 (2006.01); G02F 1/1362 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1222 (2013.01); G02F 1/1368 (2013.01); G02F 1/136286 (2013.01); H01L 27/124 (2013.01); H01L 27/127 (2013.01); H01L 27/1288 (2013.01); H01L 29/0692 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01);
Abstract

Embodiments of the invention disclose an array substrate and a method for manufacturing the same, and a display device. The method for manufacturing an array substrate comprising: forming a gate metal layer, wherein the gate metal layer comprises gate lines; film-forming an active layer and film-forming a signal line metal layer, wherein the signal line metal layer comprises data lines; and forming both a pattern of the active layer and a pattern of the signal line metal layer simultaneously using a half-tone mask process, wherein after film-forming the active layer and before film-forming the signal line metal layer, the method further comprising: hollowing out a first region of the active layer through a patterning process, wherein the first region is below the data lines in a display area, and the first region excludes portions of the active layer corresponding to overlapping regions of the data lines and the gate lines.


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