The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2015

Filed:

Jun. 12, 2014
Applicants:

Shailesh Kumar, Ghaziabad, IN;

Rishi Bhooshan, Ghaziabad, IN;

Vikas Garg, Parvatiya Vihar, IN;

Chetan Verma, Noida, IN;

Navas Khan Oratti Kalandar, Petaling Jaya, MY;

Inventors:

Shailesh Kumar, Ghaziabad, IN;

Rishi Bhooshan, Ghaziabad, IN;

Vikas Garg, Parvatiya Vihar, IN;

Chetan Verma, Noida, IN;

Navas Khan Oratti Kalandar, Petaling Jaya, MY;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/49 (2013.01); H01L 2224/4917 (2013.01); H01L 2924/30101 (2013.01);
Abstract

A semiconductor device uses insulated bond wires to connect peripheral power supply and ground bond pads on the periphery of the device to array power supply and ground bond pads located on an interior region of a integrated circuit die of the device. Power supply and ground voltages are conveyed from array bond pads using vertical vias down to one or more corresponding inner power distribution layers. The bond wire connections form rows and columns of hops constituting a mesh power grid that reduces the IR drop of the semiconductor device.


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