The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2015

Filed:

Jul. 25, 2013
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Min gi Hong, Asan-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/82 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 23/3114 (2013.01); H01L 23/3128 (2013.01); H01L 24/97 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/15151 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01);
Abstract

Disclosed are semiconductor packages and methods of fabricating the same. A method may include preparing a wiring board including a mounting region and a molding region surrounding the mounting region; forming a through-hole penetrating through the wiring board at the mounting region; mounting a semiconductor chip on the mounting region of the wiring board by a flip chip bonding method; and forming a molding covering the molding region of the wiring board and the semiconductor chip and filling the through-hole and a space between the semiconductor chip and the wiring board. The wiring board may have a first surface on which the semiconductor chip is mounted, and a second surface opposite to the first surface. A portion of the molding filling the through-hole has a surface coplanar with the second surface of the wiring board.


Find Patent Forward Citations

Hong, Min. (2015). Semiconductor package and method of fabricating the same (U.S. Patent No. 9196538). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9196538

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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